1. Field of the Invention
The present invention relates to a method of forming a semiconductor structure, and more particularly to a method of forming a semiconductor structure which can tune pitch walking issues.
2. Description of the Prior Art
With increasing miniaturization of semiconductor devices, various multi-gate MOSFET devices have been developed. The multi-gate MOSFET is advantageous for the following reasons. First of all, the fabrication of the multi-gate MOSFET devices is allowable to be integrated into traditional logic device processes, and thus is more compatible. In addition, since the three-dimensional structure of the multi-gate MOSFET increases the overlapping area between the gate and the substrate, the channel region is controlled more effectively, thereby reducing both the drain-induced barrier lowering (DIBL) effect and the short channel effect. Moreover, as the channel region is longer for the same gate length, the current between the source and the drain is increased.
A multi-gate MOSFET has a gate formed on fin-shaped structures, wherein the fin-shaped structures is formed generally through a pattern transfer technique, such as the sidewall image transfer (SIT) process. However, with the demands of miniaturizing the semiconductor devices, the width of each fin-shaped structure, as well as the spacing therebetween both shrinks dramatically. Thus, forming fin-shaped structures which can achieve the required demands under the restrictions of miniaturization, physical limitations and various processing parameters becomes an extreme challenge.